Jiayi (Tris) Tian

Email: jiayi_tian@ucsb.edu | Mobile: 805-2450298

Education

University of California, Santa Barbara Santa Barbara, CA

Department of Electrical and Computer Engineering Sept. 2023 - ongoing

￭ MS/PhD, Major in Computer Engineering

Nanjing University Nanjing, China

School of Electronic Science and Engineering Sept. 2019 - Jul. 2023

￭ B.Eng., Major in VLSI Design & System Integration

￭ Cumulative GPA: 4.51/5.0; Major GPA: 4.49/5.0 (Top 10% in the grade)

Relevant Coursework: Digital System I(96), Experiments in Digital Logical Circuits(96), Design of Deep Learning System Based on Hardware Acceleration of FPGA(92), Fundamentals of IC Design(83), VLSI DSP Architectures(89), Digital Logic and Intelligent Processor Design(87), IC design and solution(91.6), SoC Design Methodology(94)

Technical Skills

￭ Programming Languages: C/C++, Python/Pytorch, Verilog, Matlab, LaTex

￭ Hardware Design and Simulation Tools: Vivado/Vitis, Quartus, Modelsim, Design Compiler, VCS, DVE, Altium Designer, Multisim, SPICE

￭ Development Tools: VSCode, Git/Github, Bash, Jupyter Notebook

Publications

￭ Jiayi Tian, Chao Fang, Haonan Wang and Zhongfeng Wang. "BEBERT: Efficient and robust binary ensemble BERT." IEEE Conference on Acoustics, Speech, and Signal Processing (ICASSP). 2023 [accepted]

Experience

Zhang’s Group, University of California, Santa Barbara Santa Barbara, CA

Graduate Student Researcher, collaborated with Intel's Component Research June. 2023 - ongoing

￭ Constructed an end-to-end tensorized Transformer training FPGA accelerator with software and hardware co-design.

￭ Designed a hardware-friendly end-to-end tensorized Transformer training framework with 31x compression ratio without performance degradation using Python and Pytorch.

￭ Developed a synthesizable tensorized Transformer training engine using C++, including forward propagation, backward propagation, gradients computing and weight updates.

￭ Devised efficient dataflows for tensorized Transformer training with parallel and pipeline using Vitis HLS.

ICAIS Lab, Nanjing University Nanjing, China

Research Assistant. Apr. 2021- Oct. 2022

￭ Proposed Binary Ensemble BERT (BEBERT), a novel compression scheme to boost the training efficiency, model accuracy, and robustness of binary BERT for accurate and hardware-friendly inference.

￭ Developed a binary ensemble BERT finetuning algorithm to construct highly compressed BERT with 13x reduction in model size and 15x reduction in computation cost using Python and PyTorch.

￭ Published "BEBERT: Efficient and robust binary ensemble BERT" on ICASSP23.

projects

ICAIS Lab, Nanjing University Nanjing, China

Undergraduate Graduation Project. Nov. 2022- June. 2023

￭ Developed an early-exit BEBERT for efficient and accurate inference design.

￭ Accomplished an ensemble algorithm with the early-exit mechanism for binary BERT models, further reducing the computation cost by 20%~40% compared to BEBERT in the GLUE benchmark.

￭ Used Python and Pytorch to rewrite critical operations in binary BERTs for hardware accelerator design.

ICAIS Lab, Nanjing University Sept. 2021- Sept. 2022

Team Project.

￭ Designed an INT8 quantized BERT model for hardware-friendly inference using Python and PyTorch.

￭ Used Matlab to achieve critical operations (Attention, Softmax. etc.) for hardware design.

VLSI Design Course Project Mar. 2022- Jun. 2022

Individual assignment, A (top 5%)

￭ Used Synopsys's VCS, DVE and Design Compiler tools to devise, evaluate and synthesize efficient one-dimension convolution computing.

￭ Proposed three optimization methods based on basic VLSI techniques, including pipeline, parallel, and transpose, to accelerate the convolution process and reduce the area.

Verilog Design Course Project Mar. 2021- Jun. 2021

Team Project, A+

￭ Used Quartus and Intel Cyclone5 Series' FPGA to complete a VGA display clock on the monitor, which could set up time by typing on the keyboard.

￭ Analyzed the temporal logic of the VGA interface to achieve the correct time sequence and used RAM to store the address for the hands of the clock displayed on the screen.

Honors and Awards

￭ People's Scholarship, The 2nd Prize in NJU, Dec. 2022 (10%)

￭ Excellent Student, NJU, Dec. 2022(5%)

￭ Huawei "Intelligent Base" Scholarship, Dec. 2022 (<1%)

￭ Excellent Volunteer Prize on the school's 120th anniversary, Sept. 2022 (<1%)

￭ Excellent Volunteer Prize, NJU, Dec. 2021 (<1%)

￭ Jinxiao Company Scholarship, Nov. 2021 (5%)

￭ People's Scholarship, The Academic Competition Award, Nov. 2021 (5%)

￭ National Undergraduate Electronic Design Contest, The 2nd Prize in Jiangsu Province, Nov. 2021 (30%)

￭ Excellent Department Director, Student Union in Sch of Elec Sci and Eng., NJU, Oct. 2021 (15%)

￭ People's Scholarship, The 2nd Prize in NJU, Nov. 2020 (10%)

￭ National Undergraduate Electronic Design Contest, The 2nd Prize in Jiangsu Province, Oct. 2020 (30%)